The Semiconductor SIG presents...
Agilent Series Part 3 of 3
For Chris Mueth's presentation slides, Click HERE!
Cellular and Wireless LAN designs are becoming more extreme due to increasing bands, radio formats, antenna ports, and frequency range. All of these conspire to make system Integration and validation a train wreck in the design flow. What can be done to mitigate the volume of work and relieve this critical choke point? Potential solutions include moving test upstream so only added value in each stage is tested, providing more system context earlier in the design flow and finding less expensive ways to do “just enough” validation. The panel will explore how industry is solving the tough integration/validation challenges.
MODERATOR:
Dave Shepard
Vice President and General Manager, High Performance Solutions Business Unit, Peregrine Semiconductor
SPEAKER:
Chris Mueth
Modular Software Infrastructure Planning Manager, Agilent Technologies
SIG CO-CHAIRS:
Dr. Jim Cable, CEO, Peregrine Semiconductor
Dr. Anton Monk, Co-Founder & VP Technology, Entropic Communications
Dr. Roberto Aiello, Standards & Technology Development, Itron
Rory Moore, CEO, CommNexus & Founder, Peregrine Semiconductor & Silicon Wave
Dave Shephard, VP & General Manager, Peregrine Semiconductor
DATE:
October 10, 2012
TIME:
5:30PM Registration/Networking/Refreshments
6:00PM Program Begins
7:30PM Program Ends
LOCATION:
6290 Sequence Drive
San Diego, California 92121
COST:
Entropic and CommNexus present the third part of this series at NO COST to the community!
Questions? Contact Brittany Bjerke at bbjerke@commnexus.org
As a closing of the Agilent series, this event will be presented at NO COST to the community!
**Please note event location change!**
Now located in the heart of Sorrento Valley at Entropic Communications!
Achieving Hardware Validation During Design
Agilent Series Part 3 of 3
For Chris Mueth's presentation slides, Click HERE!
Cellular and Wireless LAN designs are becoming more extreme due to increasing bands, radio formats, antenna ports, and frequency range. All of these conspire to make system Integration and validation a train wreck in the design flow. What can be done to mitigate the volume of work and relieve this critical choke point? Potential solutions include moving test upstream so only added value in each stage is tested, providing more system context earlier in the design flow and finding less expensive ways to do “just enough” validation. The panel will explore how industry is solving the tough integration/validation challenges.MODERATOR:
Dave Shepard
Vice President and General Manager, High Performance Solutions Business Unit, Peregrine Semiconductor
David (Dave) Shepard has served as the Vice President and General Manager, High Performance Solutions Business Unit at Peregrine Semiconductor since April 2010. From October 2003 to August 2009, Mr. Shepard served as President and Chief Executive Officer of Sequoia Communications, an early stage company specializing in RF transceivers for mobile handsets. Prior to that, he held various positions at Texas Instruments, including General Manager of the Wireless Infrastructure Business Unit. Mr. Shepard received a B.A. from Lawrence University and an M.S.E.E. from the University of Wisconsin, Madison.
SPEAKER:
Chris Mueth
Modular Software Infrastructure Planning Manager, Agilent Technologies
Chris Mueth is the Modular Software Infrastructure Planning Manager for Agilent EEsof EDA, responsible for a wide range of software infrastructure components ranging from simulators, to model sets, to instrument links. Chris worked within Agilent Technologies in several roles in Agilent EEsof since 2000, including World Wide Business Development Manager, and Product Marketing Manager. Prior to joining Agilent, Chris held high level R&D management, development engineering, and ATE engineering positions with several companies, developing commercial and defense oriented communications subsystems and components, and commercializing newly developed technologies. Chris holds an MBA with Pepperdine University, and an engineering degree at California State University Northridge.
SIG CO-CHAIRS:
Dr. Jim Cable, CEO, Peregrine Semiconductor
Dr. Anton Monk, Co-Founder & VP Technology, Entropic Communications
Dr. Roberto Aiello, Standards & Technology Development, Itron
Rory Moore, CEO, CommNexus & Founder, Peregrine Semiconductor & Silicon Wave
Dave Shephard, VP & General Manager, Peregrine Semiconductor
DATE:
October 10, 2012
TIME:
5:30PM Registration/Networking/Refreshments
6:00PM Program Begins
7:30PM Program Ends
LOCATION:
6290 Sequence Drive
San Diego, California 92121
COST:
Entropic and CommNexus present the third part of this series at NO COST to the community!
**THERE WILL BE AN 'AGILENT DRAWING GIVEAWAY' AT THIS EVENT!**
The Agilent U1242B 4-digit handheld digital multimeter (DMM) is designed for quick checks and fixes in the installation and maintenance of machinery, facility and electrical systems. Key capabilities include the switch counter for the detection of glitches on facility switch and relay systems. The harmonic ratio function helps detect the presence of harmonics in AC supplies that can lead to overheating of motors, generators and transformers. The U1242B also enables dual and differential temperature measurements for heating, ventilation and air-conditioning (HVAC) systems. Monitoring differential temperature in real-time is especially useful in making sure that HVAC components in the system are cooling or heating the way they should with respect to time. With the U1242B, you can perform inspections quickly and conveniently with the same troubleshooting tool that you carry on your daily rounds.
Check more, fix more
Check more, fix more
- 10,000-count display
- 0.09% basic DC voltage accuracy and true RMS measurement
- Basic functions: DCV, DCI, ACV, ACI, resistance, frequency, continuity, diode test
- Advanced functions: capacitance, switch counter, harmonic ratio, dual and differential temperature, data logging to DMM (up to 200 points)
To view part one of this series, CLICK BELOW:
Anticipate System Level Design Challenges:
Bridging Design Domain Gaps
(Part 1)
To view part two of this series, CLICK BELOW:
Accelerate 3D-IC integration for RF applications:
More than Moore – a necessity for RF?
(Part 2)
Anticipate System Level Design Challenges:
Bridging Design Domain Gaps
(Part 1)
To view part two of this series, CLICK BELOW:
Accelerate 3D-IC integration for RF applications:
More than Moore – a necessity for RF?
(Part 2)
SIG EVENT SPONSORED BY:
Questions? Contact Brittany Bjerke at bbjerke@commnexus.org
Date:
Wednesday, October 10, 20125:30 PM - 7:30 PM
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